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HT48R05A-1 8-bit otp microcontroller 1 november 29, 2000 general description the device is an 8-bit high performance risc-like microcontroller designed for multi - ple i/o product applications. the device is par - ticularly suitable for use in products such as remote controllers, fan/light controllers, wash- ing machine controllers, scales, toys and vari- ous subsystem controllers. a halt feature is included to reduce power consumption. the program and option memories can be elec - trically programmed, making the microcontrol- ler suitable for use in product development. features operating voltage: f sys =4mhz: 3.3v~5.5v f sys =8mhz: 4.5v~5.5v 13 bidirectional i/o lines an interrupt input shared with an i/o line 8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler on-chip crystal and rc oscillator watchdog timer 512 14 program memory prom 32 8 data memory ram buzzer driving pair and pfd supported halt function and wake-up feature reduce power consumption up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v all instructions in one or two machine cycles 14-bit table read instruction two-level subroutine nesting bit manipulation instruction 63 powerful instructions low voltage reset function 16-pin ssop package 18-pin dip/sop package
block diagram pin assignment HT48R05A-1 2 november 29, 2000

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pin description pin no. pin name i/o rom code option description 4~1, 18~15 pa0~pa7 i/o pull-high* wake-up bidirectional 8-bit input/output port. each bit can be configured as wake-up input by rom code option. software instructions determine the cmos output or schmitt trigger input with a pull-high resistor (deter - mined by pull-high options). 7 6 5 pb0/bz pb1/bz pb2 i/o pull-high* i/o or bz/bz bidirectional 3-bit input/output port. software in - structions determine the cmos output or schmitt trigger input with a pull-high resistor (determined by pull-high options). the pb0 and pb1 are pin-shared with the bz and bz , respectively. once the pb0 and pb1 are selected as buzzer driving outputs, the output signals come from an internal pfd generator (shared with timer/event counter). 8 vss negative power supply, ground 9 10 pc0/int pc1/tmr i/o pull-high* bidirectional i/o lines. software instructions deter - mine the cmos output or schmitt trigger input with a pull-high resistor (determined by pull-high op - tions). the external interrupt and timer input are pin-shared with the pc0 and pc1, respectively. the external interrupt input is activated on a high to low transition. 11 res i schmitt trigger reset input. active low 12 vdd positive power supply 13 14 osc1 osc2 i o crystal or rc osc1, osc2 are connected to an rc network or crys- tal (determined by rom code option) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. * all pull-high resistors are controlled by an option bit. absolute maximum ratings supply voltage ...............v ss 0.3v to v ss +5.5v storage temperature................. 50 cto125 c input voltage .................v ss 0.3v to v dd +0.3v operating temperature .............. 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maxi - mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo - sure to extreme conditions may affect device reliability. HT48R05A-1 3 november 29, 2000
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 operating voltage f sys =4mhz 3.3 5.5 v v dd2 operating voltage f sys =8mhz 4.5 5.5 v i dd1 operating current (crystal osc) 3.3v no load, f sys =4mhz 12ma 5v 24ma i dd2 operating current (rc osc) 3.3v no load, f sys =4mhz 12ma 5v 24ma i dd3 operating current (crystal osc) 5v no load, f sys =8mhz 510ma i stb1 standby current (wdt enabled) 3.3v no load, system halt 5 a 5v 10 a i stb2 standby current (wdt disabled) 3.3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o ports, tmr and int 3.3v 0 0.2v dd v 5v 0 0.2v dd v v ih1 input high voltage for i/o ports, tmr and int 3.3v 0.8v dd v dd v 5v 0.8v dd v dd v v il2 input low voltage (res ) 3.3v 0 0.4v dd v 5v 0 0.4v dd v v ih2 input high voltage (res ) 3.3v 0.9v dd v dd v 5v 0.9v dd v dd v i ol i/o port sink current 3.3v v ol =0.1v dd 48 ma 5v v ol =0.1v dd 10 20 ma i oh i/o port source current 3.3v v oh =0.9v dd 2 4 ma 5v v oh =0.9v dd 5 10 ma r ph pull-high resistance 3.3v 40 60 80 k 5v 10 30 50 k v lvr low voltage reset 3.1 3.2 3.3 v HT48R05A-1 4 november 29, 2000
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 3.3v 400 4000 khz 5v 400 8000 khz f sys2 system clock (rc osc) 3.3v 400 4000 khz 5v 400 4000 khz f timer timer i/p frequency (tmr) 3.3v 0 4000 khz 5v 0 4000 khz t wdtosc watchdog oscillator 3.3v 43 86 168 s 5v 35 65 130 s t wdt1 watchdog time-out period (rc) 3.3v without wdt prescaler 11 22 43 ms 5v 9 17 35 ms t wdt2 watchdog time-out period (system clock) without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period power-up, reset or wake-up from halt 1024 t sys t int interrupt pulse width 1 s HT48R05A-1 5 november 29, 2000
HT48R05A-1 6 november 29, 2000 functional description execution flow the system clock for the microcontroller is de - rived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an in - struction cycle while decoding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruction to ef - fectively execute in a cycle. if an instruction changes the program counter, two cycles are re - quired to complete the instruction. program counter pc the program counter (pc) controls the se - quence in which the instructions stored in pro - gram prom are executed and its contents specify full range of program memory. after accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. the program counter then points to the memory word contain- ing the next instruction code. when executing a jump instruction, conditional skip execution, loading pcl register, subrou - tine call, initial reset, internal interrupt, exter - nal interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruc - tions. once the condition is met, the next in - struction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper in - struction. otherwise proceed with the next in - struction. the lower byte of the program counter (pcl) is a readable and writable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an addi - tional dummy cycle is required. program memory prom the program memory is used to store the pro - gram instructions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 512 14 bits, addressed by the program counter and table pointer.

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HT48R05A-1 7 november 29, 2000 certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initializa - tion. after chip reset, the program always be - gins execution at location 000h. location 004h this area is reserved for the external inter - rupt service program. if the int input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event coun - ter interrupt service program. if a timer inter - rupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008h. table location any location in the prom space can be used as look-up tables. the instructions "tabrdc [m]" (the current page, 1 page=256 words) and "tabrdl [m]" (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of tblh, and the remaining 2 bits are read as "0". the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), which indicates the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service mode program counter *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0 0 0 0 0 0 0 0 0 external interrupt 0 0 0 0 0 0 1 0 0 timer/event counter overflow 0 0 0 0 0 1 0 0 0 skip pc+2 loading pcl *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *8~*0: program counter bits s8~s0: stack register bits #8~#0: instruction code bits @7~@0: pcl bits = = = >1/% 66= 66= #*+#', $,*#2 $?1&$.1/1'(1@'/1*. #*+#', 9 /$ #. ' (. /$ ##- 0 / - > #* - /1. $ 1, $# ?$./ *-./$#./$##-0/ ->#*-/1.$ **<:-0'>($ **<:-0'>($7
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HT48R05A-1 8 november 29, 2000 instruction table location *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *8~*0: table location bits p8: current program counter bits @7~@0: table pointer bits routine) both employ the table read instruc - tion, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read in - struction in the main routine and the isr si - multaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the inter - rupt is supposed to be disabled prior to the ta - ble read instruction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to com - plete the operation. these areas may function as normal program memory depending upon the requirements. stack register stack this is a special part of the memory which is used to save the contents of the program coun - ter (pc) only. the stack is organized into 2 lev - els and is neither part of the data nor part of the program space, and is neither readable nor writable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt ac- knowledgment, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro- gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhib - ited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow allowing the programmer to use the structure more eas - ily. in a similar case, if the stack is full and a "call" is subsequently executed, stack over - flow occurs and the first entry will be lost (only the most recent 2 return addresses are stored). data memory ram the data memory is designed with 49 8 bits. the data memory is divided into two func - tional groups: special function registers and general purpose data memory (32 8). most are read/write, but some are read only. the special function registers include the indi - rect addressing register (00h), timer/event counter (tmr;0dh), timer/event counter con - trol register (tmrc;0eh), program counter lower-order byte register (pcl;06h), memory pointer register (mp;01h), accumulator (acc;05h), table pointer (tblp;07h), table higher-order byte register (tblh;08h), status register (status;0ah), interrupt control reg - ister (intc;0bh), watchdog timer option set - ting register (wdts;09h), i/o registers (pa;12h, pb;14h, pc;16h) and i/o control registers (pac;13h, pbc;15h, pcc;17h). the remaining space before the 60h is reserved for future expanded usage and reading these loca- tions will get "00h". the general purpose data memory, addressed from 60h to 7fh, is used for data and control information under in- struction commands.
HT48R05A-1 9 november 29, 2000 all of the data memory areas can handle arith - metic, logic, increment, decrement and rotate operations directly. except for some dedicated bits, each bit in the data memory can be set and reset by "set [m].i" and "clr [m].i". they are also indirectly accessible through memory pointer register (mp;01h). indirect addressing register location 00h is an indirect addressing register that is not physically implemented. any read/write operation of [00h] accesses data mem - ory pointed to by mp (01h). reading location 00h itself indirectly will return the result 00h. writ - ing indirectly results in no operation. the memory pointer register mp (01h) is a 7-bit register. the bit 7 of mp is undefined and reading will return the result 1 . any writing operation to mp will only transfer the lower 7-bit data to mp. accumulator the accumulator is closely related to alu oper - ations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operations. the alu provides the following func- tions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data op - eration but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pd), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pd flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pd flag. in addition opera - 5 $.$#'( -#0*%$ 7
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HT48R05A-1 10 november 29, 2000 tions related to the status register may give different results from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the "clr wdt" or "halt" instruction. the pd flag can be affected only by executing the "halt" or "clr wdt" instruction or a sys - tem power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or executing the subroutine call, the status reg - ister will not be pushed onto the stack automat - ically. if the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. interrupt the device provides an external interrupt and internal timer/event counter interrupts. the interrupt control register (intc;0bh) con - tains the interrupt control bits to set the en - able/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the emi bit). this scheme may prevent any fur - ther interrupt nesting. other interrupt re - quests may happen during this interval but only the interrupt request flag is recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the correspond - ing bit of intc may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related in - terrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up ca - pability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a sub - routine at specified location in the program memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the in - terrupt service program which corrupts the de - sired control sequence, the contents should be saved in advance. external interrupts are triggered by a high to low transition of int and the related interrupt labels bits function c 0 c is set if the operation results in a carry during an addition operation or if a bor- row does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z 2 z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared by system power-up or executing the "clr wdt" instruction. pd is set by executing the "halt" instruction. to 5 to is cleared by system power-up or executing the "clr wdt" or "halt" in - struction. to is set by a wdt time-out. 6 undefined, read as "0" 7 undefined, read as "0" status register
HT48R05A-1 11 november 29, 2000 request flag (eif; bit 4 of intc) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a sub - routine call to location 04h will occur. the in - terrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf; bit 5 of intc), caused by a timer overflow. when the interrupt is enabled, the stack is not full and the tf bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (tf) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other interrupt acknowledgments are held until the "reti" instruction is executed or the emi bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, "ret" or "reti" may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are en- abled. in the case of simultaneous requests the following table shows the priority that is ap - plied. these can be masked by resetting the emi bit. no. interrupt source priority vector a external interrupt 1 04h b timer/event counter overflow 2 08h the timer/event counter interrupt request flag (tf), external interrupt request flag (eif), en - able timer/event counter bit (eti), enable ex - ternal interrupt bit (eei) and enable master interrupt bit (emi) constitute an interrupt con - trol register (intc) which is located at 0bh in the data memory. emi, eei, eti are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (tf, eif) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the "call subroutine" within the inter - rupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con trolled, the original control sequence will register bit no. label function intc (0bh) 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei controls the external interrupt (1= enabled; 0= disabled) 2 eti controls the timer/event counter interrupt (1= enabled; 0= disabled) 3 unused bit, read as "0" 4 eif external interrupt request flag (1= active; 0= inactive) 5tf internal timer/event counter request flag (1= active; 0= inactive) 6 unused bit, read as "0" 7 unused bit, read as "0" intc register
HT48R05A-1 12 november 29, 2000 be damaged once the "call" operates in the in - terrupt subroutine. oscillator configuration there are two oscillator circuits in the microcontroller. both are designed for system clocks, namely the rc oscillator and the crystal oscillator, which are determined by the rom code option. no matter what oscillator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and ignores an external signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vdd is required and the resistance must range from 51k to 1m . the system clock, divided by 4, is available on osc2, which can be used to synchronize exter- nal logic. the rc oscillator provides the most cost effective solution. however, the frequency of oscillation may vary with vdd, tempera- tures and the chip itself due to process varia- tions. it is, therefore, not suitable for timing sensitive operations where an accurate oscilla- tor frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feed - back and phase shift required for the oscillator, and no other external components are required. instead of a crystal, a resonator can also be con - nected between osc1 and osc2 to get a fre - quency reference, but two external capacitors in osc1 and osc2 are required (if the oscillat - ing frequency is less than 1mhz). the wdt oscillator is a free running on-chip rc oscillator, and no external components are re - quired. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approxi - mately 65 s/5v. the wdt oscillator can be dis - abled by rom code option to conserve power. watchdog timer wdt the clock source of wdt is implemented by a dedicated rc oscillator (wdt oscillator) or in - struction clock (system clock divided by 4), de - cided by rom code option. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by a rom code option. if the watchdog timer is disabled, all the execu- tions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 65 s/5v normally) is selected, it is first divided by 256 (8-stage) to get the nomi- nal time-out period of approximately 16.6ms/5v. this time-out period may vary with temperatures, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give differ - #2%/'( %&1(('/*# %&1(('/*#
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HT48R05A-1 13 november 29, 2000 ent time-out periods. if ws2, ws1, and ws0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.2s/5v. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. the high nib - ble and bit 3 of the wdts are reserved for user's defined flags, which can be used to indicate some specified status. if the device operates in a noisy environment, us - ing the on-chip rc oscillator (wdt osc) is strongly recommended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts register the wdt overflow under normal operation will initialize "chip reset" and set the status bit "to". but in the halt mode, the overflow will initialize a "warm reset" and only the pc and sp are reset to zero. to clear the contents of wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res ), software instruction and a "halt" in - struction. the software instruction include "clr wdt" and the other set "clr wdt1" and "clr wdt2". of these two types of instruc - tion, only one can be active depending on the rom code option "clr wdt times selection option". if the "clr wdt" is selected (i.e. clrwdt times equal one), any execution of the "clr wdt" instruction will clear the wdt. in the case that "clr wdt1" and "clr wdt2" are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. power down operation halt the halt mode is initialized by the "halt" in - struction and results in the following... the system oscillator will be turned off but the wdt oscillator keeps running (if the wdt oscillator is selected). the contents of the on chip ram and regis - ters remain unchanged. wdt and wdt prescaler will be cleared and recounted again (if the wdt clock is from the wdt oscillator). all of the i/o ports maintain their original sta - tus. the pd flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge signal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow performs a "warm re - set". after the to and pd flags are examined, the reason for chip reset can be determined. the pd flag is cleared by system power-up or executing the "clr wdt" instruction and is set when executing the "halt" instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the pc and sp; the others keep their original status. the port a wake-up and interrupt methods can be considered as a continuation of normal exe- cution. each bit in port a can be independently selected to wake up the device by the rom code option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. if it is awakening from an inter - rupt, two sequences may happen. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the inter - rupt is enabled and the stack is not full, the reg - ular interrupt response takes place. if an interrupt request flag is set to "1" before enter - ing the halt mode, the wake-up function of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (sys - tem clock period) to resume normal operation. in other words, a dummy period will be inserted
HT48R05A-1 14 november 29, 2000 after wake-up. if the wake-up results from an interrupt acknowledgment, the actual inter - rupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is fin - ished. to minimize power consumption, all the i/o pins should be carefully managed before enter - ing the halt status. reset there are three ways in which a reset can oc - cur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a "warm reset" that resets only the pc and sp, leaving the other circuits in their origi - nal state. some registers remain unchanged during other reset conditions. most registers are reset to the "initial condition" when the re - set conditions are met. by examining the pd and to flags, the program can distinguish be- tween different "chip resets". to pd reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1u wdt time-out during normal opera- tion 1 1 wdt wake-up halt note: "u" means "unchanged" to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will enable the sst delay. the functional unit chip reset status are as shown below. pc 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode sp points to the top of the stack / 1, $:*-/ 410$%$/ reset timing chart reset circuit " '#, $%$/ " = *(3 $%$/ 2%/$, $%$/ :>1/ 100($ *-./$# reset configuration
HT48R05A-1 15 november 29, 2000 the states of the registers is summarized in the table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmrc 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu program counter 000h 000h 000h 000h 000h mp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu pbc ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu pc ------11 ------11 ------11 ------11 ------uu pcc ------11 ------11 ------11 ------11 ------uu note: "*" means "warm reset" "u" means "unchanged" "x" means "unknown"
HT48R05A-1 16 november 29, 2000 timer/event counter a timer/event counter (tmr) is implemented in the microcontroller. the timer/event counter contains an 8-bit programmable count-up coun - ter and the clock may come from an external source or the system clock. using the internal system clock, there is only one reference time-base. the internal clock source comes from f sys . the external clock in - put allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are 2 registers related to the timer/event counter; tmr ([0dh]), tmrc ([0eh]). two phys - ical registers are mapped to tmr location; writ - ing tmr makes the starting value be placed in the timer/event counter preload register and reading tmr gets the contents of the timer/event counter. the tmrc is a timer/event counter con - trol register, which defines some options. label (tmrc) bits function psc0~psc2 0~2 to define the prescaler stages, psc2, psc1, psc0= 000: f int =f sys /2 001: f int =f sys /4 010: f int =f sys /8 011: f int =f sys /16 100: f int =f sys /32 101: f int =f sys /64 110: f int =f sys /128 111: f int =f sys /256 te 3 to define the tmr active edge of timer/event counter (0=active on low to high; 1=active on high to low) ton 4 to enable/disable timer counting (0=disabled; 1=enabled) 5 unused bits, read as"0" tm0 tm1 6 7 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc register -(%$" 13/4 $'%-#$, $./ *3$ *./#*( 1, $# ?$./ *-./$# #$(*'3 $+1%/$# 1, $#$?$./ *-./$# '/'-% $(*'3 ?$#)(*a /*./$##-0/
:%/'+$0#$%&'($# : ) )
timer/event counter
HT48R05A-1 17 november 29, 2000 the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr) pin. the timer mode functions as a normal timer with the clock source coming from the f int clock. the pulse width measurement mode can be used to count the high or low level du - ration of the external signal (tmr). the counting is based on the f int clock. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffh. once overflow occurs, the coun - ter is reloaded from the timer/event counter preload register and generates the interrupt re - quest flag (tf; bit 5 of intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr has received a transient from low to high (or high to low if the te bits is "0") it will start counting until the tmr returns to the original level and resets the ton. the measured result will remain in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measure- ment will function again as long as it receives further transient pulse. note that, in this oper- ating mode, the timer/event counter starts counting not according to the logic level but ac- cording to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and is- sues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton will be cleared automatically af - ter the measurement cycle is completed. but in the other two modes the ton can only be reset by instructions. the overflow of the timer/event counter is one of the wake-up sources. no mat - ter what the operation mode is, writing a 0 to eti can disable the interrupt service. in the case of timer/event counter off condi - tion, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload reg - ister. the timer/event counter will still operate until overflow occurs. when the timer/event counter (reading tmr) is read, the clock will be blocked to avoid errors. as clock blocking may re - sults in a counting error, this must be taken into consideration by the programmer. the bit0~bit2 of the tmrc can be used to de - fine the pre-scaling stages of the internal clock sources of timer/event counter. the definitions are as shown. the overflow signal of timer/event counter can be used to generate pfd signals for buzzer driving. input/output ports there are 13 bidirectional input/output lines in the microcontroller, labeled from pa to pc, which are mapped to the data memory of [12h], [14h] and [16h] respectively. all of these i/o ports can be used for input and output operations. for in - put operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction "mov a,[m]" (m=12h, 14h or 16h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc) to control the input/output configu- ration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfig- ured dynamically (i.e. on-the-fly) under soft- ware control. to function as an input, the corresponding latch of the control register must write "1". the input source also depends on the control register. if the control register bit is "1", the input will read the pad state. if the control register bit is "0", the contents of the latches will move to the internal bus. the latter is pos - sible in the "read-modify-write" instruction. for output function, cmos is the only configu - ration. these control registers are mapped to locations 13h, 15h and 17h. after a chip reset, these input/output lines re - main at high levels or floating state (dependent on pull-high options). each bit of these in -
HT48R05A-1 18 november 29, 2000 put/output latches can be set or cleared by "set [m].i" and "clr [m].i" (m=12h, 14h or 16h) in - structions. some instructions first input data and then fol - low the output operations. for example, "set [m].i", "clr [m].i", "cpl [m]", "cpla [m]" read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accu - mulator. each line of port a has the capability of wak - ing-up the device. the highest 6-bit of port c and 5 bits of port b are not physically implemented; on reading them a "0" is returned whereas writ - ing then results in a no-operation. see applica - tion note. there is a pull-high option available for all i/o lines. once the pull-high option is selected, all i/o lines have pull-high resistors. otherwise, the pull-high resistors are absent. it should be noted that a non-pull-high i/o line operating in input mode will cause a floating state. the pb0 and pb1 are pin-shared with bz and bz signal, respectively. if the bz/bz option is selected, the output signal in output mode of pb0/pb1 will be the pfd signal generated by timer/event counter overflow signal. the input mode always remaining its original functions. once the bz/bz option is selected, the buzzer output signals are controlled by pb0 data regis - ter only. the i/o functions of pb0/pb1 are as shown below. pb0i/o iiiioooooo pb1 i/o i o o o i i i o o o pb0/pb1 mode x cbbcbbcbb pb0 data x x 0 1 d 0 1 d 0 01 pb1 data x d xxxxxd 1 xx pb0 pad status iiiid0bd 0 0b pb1 pad status i d 0 b i i i d 1 0b note: i: input; o: output; d, d 0 ,d 1 : data; b: buzzer option, bz or bz ; x: don't care c: cmos output
7 d . (2 8 )*# .(2 )* # . (2 2%/$, " '<$:-0 7 *.(28 $'3 '/' $+1%/$# 7 d . (2 8 e ! e e ! e *./#*( 1/ '/'-% " #1/$ *./#*( $+1%/$# 410 $%$/ $'3 *./#*( $+1%/$# " #1/$ '/' $+1%/$# '/'1/ f )* # * . (2 d f )* # * . (2 d& * . /#* (f 3 ' /' #$ + 1% /$ # input/output ports
HT48R05A-1 19 november 29, 2000 the pc0 and pc1 are pin-shared with int , tmr and pins respectively. it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. rom code option the following table shows all kinds of rom code option in the microcontroller. all of the rom code options must be defined to ensure proper system functioning. items option 1 wdt clock source: wdtosc/f tid 2 wdt enable/disable: enable/disable 3 lvd enable/disable: disable/enable 4 clrwdt instruction(s): one/two clear wdt instruction(s) 5 system oscillator: rc/crystal 6 pull-high resistors (pa~pc): none/pull-high 7 bz option: disable/enable 8 pa0~pa7 wake-up: disable/enable 9 lock: unlock/lock prom programming and verification the program memory used in the microcontroller is arranged into a 512 14 bits program memory and a 3 8 bits option memory. the program code and option code are stored in the program and option memories. the pro - gramming of memories can be summarized in nine steps as described below: power on (v dd =6.25v) set vpp (res ) to 12.5v set cs (pa5) to low let pa3~pa0 (ad3~ad0) be the address and data bus and the pa4 (clk) be the clock input. the data on the ad3~ad0 pins will be clocked into or out of the microcontroller on the falling edge of pa4 (clk) for otp programming and verification. the address data contains the code address (11 bits) and two option bits. a complete write cycle will contain four clk cycles. the first cycle, bits 0~3 of the address are latched into the device. the second and third cycles, bits 4~7 and bits 8~9 are latched respectively. the fourth cycle, bit 2 is the tsel option bit and bit 3 is the osel option bit. bits 2~3 in the third cycle and bits 0~1 in the fourth cycle are unde - fined. if the tsel is "1" and the osel is "0", the test memory will be read. if the tsel is "0" and the osel is "1", the option memory will be accessed. if both the tsel and osel are "0", the program memory will be managed. the code data is 14 bits wide. a complete read/write cycle contains four clk cycles. in the first cycle, bits 0~3 of the code data are ac - cessed. in the second and third, bits 4~7 and bits 8~11 are accessed respectively. in the fourth cycle, bits 12~13 are accessed. bits 14~15 are undefined. during code verification, reading will return the result "00". select the tsel and osel to program and verify the program memory and option memory. use the r/w (pa6) to select between programming or verification. the address is incremented by one automati- cally after a code verification cycle. if the dis- continued address programming or verification is accomplished, the automatic ad- dressing increment is disabled. for the discon - tinued address programming and verification, the cs pin must return to high level for a pro - gramming or verification cycle, that is, if a dis - continued address is managed, the programming or verification cycle must be in - terrupted and restarted as well.
HT48R05A-1 20 november 29, 2000 " !

1.&#$%1.+'-/*, '/1&'((2 $ #1)1& ' /1* . $ #1)1& ' /1* . successive verification the related pins of otp programming and veri - fication are listed in the following table. pin name function description pa0 ad0 bit 0 of address/data bus pa1 ad1 bit 1 of address/data bus pa2 ad2 bit 2 of address/data bus pa3 ad3 bit 3 of address/data bus pa4 clk serial clock input for ad - dress and data pa5 cs chip select, active low pa6 r/w read/write control input res vpp programming the power supply the timing charts of programming and verifica - tion are as shown. there is a lock signal for code protection. if the lock is "1", reading the code will return the result "1". however, if the lock is "0", the code protection is disabled and the code can be read always until the lock is programmed as "1".
HT48R05A-1 21 november 29, 2000 " !

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instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to register with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1(1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z HT48R05A-1 24 november 29, 2000
mnemonic description instruction cycle flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none HT48R05A-1 25 november 29, 2000
mnemonic description instruction cycle flag affected table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pd to (4) ,pd (4) to (4) ,pd (4) none none to,pd note: x: 8 bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed one more cycle (four system clocks). (2) : if a skipping to next instruction occurs, the execution cycle of instructions will be delayed one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to is set and the pd is cleared. otherwise the to and pd flags remain unchanged. HT48R05A-1 26 november 29, 2000
instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. operation acc
acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. operation [m]
acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc
acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc
acc+x affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 27 november 29, 2000
addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m]
acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc
acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logi - cal_and operation. the result is stored in the accumulator. operation acc
acc and x affected flag(s) tc2 tc1 to pd ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and operation. the result is stored in the data memory. operation [m]
acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 28 november 29, 2000
call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this ad - dress. operation stack
pc+1 pc
addr affected flag(s) tc2 tc1 to pd ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m]
00h affected flag(s) tc2 tc1 to pd ov z ac c clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i
0 affected flag(s) tc2 tc1 to pd ov z ac c clr wdt clear watchdog timer description the wdt and the wdt prescaler are cleared (re-counting from 0). the power down bit (pd) and time-out bit (to) are cleared. operation wdt and wdt prescaler
00h pd and to
0 affected flag(s) tc2 tc1 to pd ov z ac c 00 HT48R05A-1 29 november 29, 2000
clr wdt1 preclear watchdog timer description the td, pd flags, wdt and the wdt prescaler has cleared (re-counting from 0), if the other preclear wdt instruction has been executed. only exe - cution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the to and pd flags remain unchanged. operation wdt and wdt prescaler
00h* pd and to
0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* clr wdt2 preclear watchdog timer description the to, pd flags, wdt and the wdt prescaler are cleared (re-counting from 0), if the other preclear wdt instruction has been executed. only exe - cution of this instruction without the other preclear instruction, sets the in - dicated flag which implies this instruction has been executed and the to and pd flags remain unchanged. operation wdt and wdt prescaler
00h* pd and to
0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s comple- ment). bits which previously contained a 1 are changed to 0 and vice-versa. operation [m]
[m ] affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 30 november 29, 2000
cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s comple - ment). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc
[m ] affected flag(s) tc2 tc1 to pd ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary code decimal) code. the accumulator is divided into 2 nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumu - lator is greater than 9. the bcd adjustment is done by adding 6 to the origi - nal value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0
(acc.3~acc.0)+6, ac1=ac else [m].3~[m].0)
(acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4
acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4
acc.7~acc.4+ac1,c=c affected flag(s) tc2 tc1 to pd ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1 operation [m]
[m] 1 affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 31 november 29, 2000
deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc
[m] 1 affected flag(s) tc2 tc1 to pd ov z ac c halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc
pc+1 pd
1 to
0 affected flag(s) tc2 tc1 to pd ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m]
[m]+1 affected flag(s) tc2 tc1 to pd ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc
[m]+1 affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 32 november 29, 2000
jmp addr directly jump description bits of the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc
addr affected flag(s) tc2 tc1 to pd ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc
[m] affected flag(s) tc2 tc1 to pd ov z ac c mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc
x affected flag(s) tc2 tc1 to pd ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memory). operation [m]
acc affected flag(s) tc2 tc1 to pd ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc
pc+1 affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 33 november 29, 2000
or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memory) perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc
acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc
acc or x affected flag(s) tc2 tc1 to pd ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memory) and the accumulator per - form a bitwise logical_or operation. the result is stored in the data memory. operation [m]
acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c ret return from subroutine description the program counter is restored from the stack. this i s a 2 cycle instruction. operation pc
stack affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 34 november 29, 2000
ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. operation pc
stack acc
x affected flag(s) tc2 tc1 to pd ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). operation pc
stack emi
1 affected flag(s) tc2 tc1 to pd ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 ro - tated into bit 0. operation [m].(i+1)
[m].i; [m].i:bit i of the data memory (i=0~6) [m].0
[m].7 affected flag(s) tc2 tc1 to pd ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1)
[m].i; [m].i:bit i of the data memory (i=0~6) acc.0
[m].7 affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 35 november 29, 2000
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1)
[m].i; [m].i:bit i of the data memory (i=0~6) [m].0
c c
[m].7 affected flag(s) tc2 tc1 to pd ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 posi - tion. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1)
[m].i; [m].i:bit i of the data memory (i=0~6) acc.0
c c
[m].7 affected flag(s) tc2 tc1 to pd ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i
[m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7
[m].0 affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 36 november 29, 2000
rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i)
[m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7
[m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together ro - tated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i
[m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7
c c
[m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i
[m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7
c c
[m].0 affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 37 november 29, 2000
sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumula - tor. operation acc
acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. operation [m]
acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruc - tion, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m]
([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc
([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 38 november 29, 2000
set [m] set data memory description each bit of the specified data memory is set to 1. operation [m]
ffh affected flag(s) tc2 tc1 to pd ov z ac c set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i
1 affected flag(s) tc2 tc1 to pd ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the following instruction, fetched during the current instruction execu - tion, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m]
([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumula- tor. the data memory remains unchanged. if the result is 0, the following in- struction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc
([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 39 november 29, 2000
snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is re - placed to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc
acc+[m] +1 affected flag(s) tc2 tc1 to pd ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumula- tor, leaving the result in the data memory. operation [m]
acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc
acc+x +1 affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 40 november 29, 2000
swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are inter - changed, writing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0
[m].7~[m].4 acc.7~acc.4
[m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current in - struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 41 november 29, 2000
sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m]
rom code (low byte) tblh
rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m]
rom code (low byte) tblh
code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclusive_or operation and the result is stored in the accumulator. operation acc
acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 42 november 29, 2000
xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclusive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m]
acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xor a,x logical xor immediate data to the accumulator description data in the the accumulator and the specified data perform a bitwise logical exclusive_or operation. the result is stored in the accumulator. the 0 flag is affected. operation acc
acc xor x affected flag(s) tc2 tc1 to pd ov z ac c HT48R05A-1 43 november 29, 2000
HT48R05A-1 44 november 29, 2000 copyright 2000 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate technology corp. 48531 warm spring boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885

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